The development of complicated integrated circuits often requires powerful numerical simulation programs. For example, circuit simulation is an essential part in the design flow of integrated circuits, helping circuit designers to verify the functionality and performance of their designs without going through expensive fabrication processes. Examples of electronic circuit simulators include the Simulation Program with Integrated Circuit Emphasis (SPICE) developed at the University of California, Berkeley (UC Berkeley), and various enhanced versions or derivatives of SPICE, such as SPECTRE, developed by Cadence Design Systems, Inc. SPICE and its derivatives or enhanced versions will be referred to hereafter as SPICE circuit simulators, or SPICE.
An integrated circuit is a network of circuit elements such as resistors, capacitors, inductors, mutual inductors, transmission lines, diodes, bipolar junction transistors (BJT), junction field effect transistors (JFET), metal-oxide-semiconductor field effect transistors (MOSFET), metal-semiconductor field effect transistors (MESFET), thin-film transistors (TFT), etc. SPICE models a circuit in a node/element fashion, i.e., the circuit is regarded as a collection of various circuit elements connected at nodes. At the heart of SPICE is the so-called Nodal Analysis, which is accomplished by formulating nodal equations (or circuit equations) in matrix format to represent the circuit and by solving these nodal equations. The circuit elements are modeled by device models, which produce model results that are represented in the circuit equations as matrices.
A device model for modeling a circuit element, such as the SPICE model for modeling MOSFET devices, developed by UC Berkeley, typically includes model equations and a set of model parameters that mathematically represent characteristics of the circuit element under various bias conditions. For example, a circuit element with n terminals can be modeled by the following current-voltage relations:Ii=fi(V1, . . . , Vn, t) for i=1, . . . , n, where Ii represents the current entering terminal I; Vj (j=1, . . . , n) represents the voltage or terminal bias across terminal j and a reference terminal, such as the ground; and t represents the time. The Kirchhoff's Current Law implies that the current entering terminal n is given by
      I    n    =            ∑              i        =        1                    n        -        1              ⁢                  I        i            .      A conductance matrix of the circuit element is defined by:
      G    ⁡          (                        V          1                ,        …        ⁢                                  ,                  V          n                ,        t            )        :=            (                                                                  ∂                                  f                  1                                                            ∂                                  V                  1                                                                          ⋯                                                              ∂                                  f                  1                                                            ∂                                  V                  n                                                                                          ⋮                                ⋰                                ⋮                                                                              ∂                                  f                  n                                                            ∂                                  V                  1                                                                          ⋯                                                              ∂                                  f                  n                                                            ∂                                  V                  n                                                                        )        .  To model the circuit element under alternating current (AC) operations, the device model also considers the relationship between node charges and the terminal biases:Qi=qi(V1, . . . , Vn, t) for i=1, . . . , n. where Qi represents the node charge at terminal i. Thus, the capacitance matrix of the n-terminal circuit element is defined by
      C    ⁡          (                        V          1                ,        …        ⁢                                  ,                  V          n                ,        t            )        :=            (                                                                  ∂                                  q                  1                                                            ∂                                  V                  1                                                                          ⋯                                                              ∂                                  q                  1                                                            ∂                                  V                  n                                                                                          ⋮                                ⋰                                ⋮                                                                              ∂                                  q                  n                                                            ∂                                  V                  1                                                                          ⋯                                                              ∂                                  q                  n                                                            ∂                                  V                  n                                                                        )        .  
A complex integrated circuit may contain millions of circuit elements such as transistors, resistors, and capacitors. The design and simulation of such a complex integrated circuit may involve multiple teams of engineers. It is advantageous to partition the design of such complex integrated circuit using a hierarchical approach, whereby certain circuit elements are grouped together and may be reused repeatedly through the integrated circuit or in a subsequent design. A method and system for design and simulation of an integrated circuit with a hierarchical data structure are disclosed by U.S. patent application Ser. No. 10/724,277, entitled “System and Method for Simulating a Circuit Having Hierarchical Structure,” which, filed on Nov. 26, 2003 and commonly owned by Cadence Design Systems, Inc., is incorporated expressly by reference in its entirety herein.
FIG. 1 illustrates a physical representation and a hierarchical representation of a design. In the physical view, each device is realized. This is equivalent to traditional simulation technologies in which each device is usually represented by one or more differential equations which will be solved for. The much more compact hierarchical representation of a design is used commonly for schematic design representation and block modeling. With the arrival of the hierarchical-SPICE simulation paradigm, this principle of compact design representation moved also into the simulator space. The huge speed and capacity advantages of hierarchical-SPICE simulators are actually due to the compact design representation and therefore much effort is spend in the hierarchical-SPICE simulators to keep this representation as compact as possible.
Hierarchical SPICE simulation technology is targeted towards high speed and very large capacity full chip verification. It requires a hierarchical representation of the design to minimize the memory imprint and improve simulation performance. Hierarchical-SPICE simulators, such as the Ultrasim product by Cadence Design Systems, Inc, have the ability to simulate designs containing more than one billion devices. Such simulators require a hierarchical representation of the design in order to optimize the memory imprint.
Mixed-signal hardware description languages (HDLs), such as Verilog-AMS and VHDL-AMS, provide many powerful features to aid in modeling of complex mixed-signal designs. For VHDL-AMS designers, the “IEEE Standard VHDL Analog and Mixed-Signal Extensions” was published by IEEE-SA Standards Board on Dec. 23, 1999. For Verilog-AMS designers, the “Verilog-AMS Language Reference Manual” was published by Accellera International Inc. on Jan. 20, 2003. Although both these HDL languages are hierarchical in nature, they contain complex modeling features that prevent them from mapping into hierarchical representations that Hierarchical-SPICE simulators can understand. There are two key features of the HDL languages that prevent them from being represented in a Hierarchical-SPICE representation: 1) ability to refer objects out of context without having an explicit connection path; and 2) ability to create implicit instances without having users to explicitly specify them in the source. These features include Verilog-AMS out-of-module-references (OOMRs), domain-less nets, and automatic insertion of connection modules (AICMs), Verilog defined parameters (defparams), VHDL-AMS package references, VHDL-AMS entity, VHDL-AMS architecture, and VHDL-AMS instantiations.
To take advantage of the benefits of Hierarchical-SPICE simulation technology, designs written in these HDL languages need to be processed to make the modeling features compliant to requirements of Hierarchical-SPICE simulators. Therefore, there is a need for a memory-efficient way in which hierarchical units of HDL such as Verilog-AMS and VHDL-AMS are refashioned at different points in the hierarchy to reflect the presence of these complex features to allow for simulation by a Hierarchical-SPICE simulator.